? semiconductor components industries, llc, 2001 march, 2001 rev. 1 1 publication order number: and8029/d and8029/d ramp compensation for the ncp1200 prepared by: christophe basso on semiconductor introduction as any currentmode controllers, the ncp1200 can be subject to subharmonic oscillations. oscillations take place when the switchmode power supply (smps) operates in continuous conduction mode (ccm) together with a dutycycle near or greater than 50%. for discontinuous conduction mode (dcm) designs, this normally does not happen. however, at the lowest line levels and when the smps is pushed to its upper output power capability, ccm can engender these oscillations within the current loop. this application note details how to properly cure this problem by injecting the correct amount of ramp compensation. origin of the problem a currentmode power supply is a twoloop system: one loop controls the inductor peak current while the other monitors the output voltage. the current loop is actually embedded into the voltage loop which fixes the final current setpoint. in ccm operation, the action of the current loop can be compared to a sample and hold device. this sampling action creates a pair of rhp zeroes in the current loop which are responsible for the boost in gain at f switching /2 but also stress the phase lag at this point. if the gain margin is too low at this frequency, any perturbation in the current will make the system unstable since, as we said, both voltage and current loops are embedded. you can fight the problem by providing the converter with an external compensation ramp. this ramp will oppose the duty cycle action by lowering the currentloop dc gain, correspondingly increasing the phase margin at f switching /2, finally damping the high q poles in the v out /v control transfer function. as other benefits of ramp compensation, ray ridley [1] confirmed that an external ramp whose slope is equal to 50% (m c = 1.5) of the inductor downslope could nullify the audio susceptibility in a buck converter, as already calculated by holland [2]. as more external ramp is added, the low frequency pole w p moves to higher frequencies while the double poles will be split into two distinct poles. the first one will move towards lower frequencies until it joins and combines with the first low frequency pole at w p . at this point, the converter behaves as if it is operating in voltage mode. lowering the peaking a current mode controlled smps exhibits one low frequency pole, w p , and two poles which are located at f switching /2. these poles move in relation to the duty cycle and the external compensation ramp, when present. the two high frequency poles present a q that depends on the compensating ramp and the dutycycle. ridley demonstrated that the q becomes infinite at d = 0.5 with no external ramp (mc = 1), confirming the inherent instability of a ccm currentmode smps operating at a duty cycle greater than 0.5. below stands the definition of this quality coefficient: q 1 (mcd 0.5) where m c = 1 + s e /s n . s e is the external ramp slope, s n is the inductor ontime slope and d = 1 d. for designers, once the system's q has been determined, they should look for the amount of ramp compensation that will make this number equal to 1: mc 1 0.5 . 1 d . how to create a ramp? on the ncp1200, you do not have access to any oscillator sawtooth. however, you can easily charge a capacitor when the gate drive is high, and immediately discharge it when the mosfet switches off. figure 1a shows how to simply generate a sawtooth from the gate drive: figure 1a a very simple way to generate a ramp from a square wave signal. d c r drv cs radd2 radd1 r sense 2 1 150 3 http://onsemi.com application note
and8029/d http://onsemi.com 2 calculating the rc component values is a rather easy task. by drawing the smallest current from the drive to avoid increasing the standby power, r shall be of high value. if this is the case, you can consider this system as a current generator. by applying vc c it , you calculate r and c. suppose we want to create a ramp that goes up to 5.0 v when a 60 khz ncp1200 is operating at 50% dutycycle. the on time is therefore 1 260k 8.3 s . in order to not bothering the ncp1200 operation, let's select a charging current of 250 m a. with a gate plateau of 11 v, this leads to a resistor of 11 v/250 m a = 44 k w . with a charging current of 250 m a, what capacitor do we need to generate a ramp that reaches 5.0 v in 8.33 m s? well, c 250 8.33 5 416 pf . however, because the charging current varies during the ramping (we actually obtain an exponential), we will to reduce both elements to their next lower normalized values, e.g., 39 k w and 390 pf. if we feed our spice simulator with these values, figure 1b and 1c confirms the calculations: figure 1b a simple simulation schematic confirms the calculations: the capacitor voltage ramps up from a few hundred of mv up to nearly 5 .0 v. figure 1c 500m 1.50 2.50 3.50 4.50 10.0u 30.0u 50.0u 70.0u 90.0u 2.00 6.00 10.0 14.0 v ramp 2.00 r1 39k c1 390pf vdrv v ramp v drive 2 1 d1 1n4148 + by ramping from 0.6 v to 4.5 v in 8.3 m s, we have created a signal exhibiting a slope of 468 mv/ m s. awhat compensation level shall i inject?o let's suppose the following specs for our flyback converter: vhv dc = 110 v fsw = 60 khz lp = 1.8 mh h = 80% n = np:ns = 0.1 pout max = 15 w to calculate the operating dutycycle d, we need to compute the peak current authorizing a 15 w output power flow from the 1.8 mh primary inductance: pin 1 2 lpip?fsw . from our specs, we know that pin = 15/08 = 18.8 w. at the boundary between dcm and ccm, the peak current is evaluated to: ip 2pin lp fsw 590 ma . to reach this value, we need to apply vhv dc over lp during: ip lp vhv dc 9.6 s . compared to a 60 khz switching frequency, it corresponds to a 58% dutycycle or d = 0.58. the external ramp injection will keep q below 1. to adhere to this requirement, we must inject a compensating ramp mc equal to 1 0.5 . 1 d 1.9 . by applying mc definition, we can deduct the final amount of external ramp we must inject: mc 1 se sn or se (mc 1) sn . in a flyback, the on slope sn is given by the rectified dc rail applied over the primary inductance lp: sn vhv dc lp . with lp = 1.8 mh, rsense = 1.5 w and the lowest main equals 110 v, then sn = 91.5 mv/ m s once reflected in volts over rsense. to get the final level of ramp compensation, let's compute se by: se (mc 1) sn or 82 mv s . to obtain this ramp from our ramping generator, we must create a division ratio of 0.082/468 or 175 m. if we select a 10 k w resistor to convey the current sense information, then the ramp resistor is calculated using: 10 k 0.175 10 k 0.175 or 47 k in this example. simulation of the converter to check our calculation, we can use the ncp1200 spice model. figure 2a portrays the application schematic for this converter with intusoft's isspice4 model version:
and8029/d http://onsemi.com 3 figure 2a the currentmode smps built with the ncp1200 spice model. r clp 22 k x4 moc8101 628 7 17 31 v out x6 mtp6n60m d3 mur160 + 1 2 3 4 8 7 6 5 d2 1n4148 ncp1200 d1 1n964 vfb v clamp r9 39 k c6 390 pf v adj x2 ncp1200 fs = 60 k v sum v ramp r comp 1 meg r conv 10 k c vcc 22 m f i c = 12.1 r5 100 m c lp 10 nf v cc r3 200 m i prim l p 1.8 mh + i drain v sense r sense 1.5 i sec v sec c3 10 n i clamp l5 30 m h i startup i ripple 1 l1 10 m h r16 10 m i out r17 300 m c1 220 m f i c = 13.5 v drain c2 220 m f i c = 13.5 x1 xfmr ratio = 0.1 r load 12 drv r15 470 v input 110 + 1 9 12 8 5 21 15 13 14 19 16 23 32 10 11 18 20 4 r4 100 m + d4 1nxxxxx bv = 60 +
and8029/d http://onsemi.com 4 the system enters ccm for a load of 12 w and subharmonic oscillations take place, as shown by figure 2b. measurements on the board confirm the presence of these unwanted oscillations (figure 2c). rcomp was kept to a high value to suppress any compensating action. figure 2b oscillations take place when entering ccm with a dutycycle greater than 50% as confirmed by both models and measurements. figure 2c 100m 100m 300m 500m 700m 1.020m 1.030m 1.040m 1.050m 1.060m 50.0 50.0 150 250 350 primary current drain voltage let's now diminish rcomp to 47 k w as previously calculated and run a new simulation. results are depicted by figure 2d and confirmed by figure 2e: figure 2d the right amount of ramp compensation stabilizes the converter (2d simulated, 2c measured). figure 2e 50.0 1.01m 1.03m 1.05m 1.07m 1.09m 100m 100m 300m 500m 700m 1.01m 1.03m 1.05m 1.07m 1.09m 50.0 150 250 350 primary current drain voltage
and8029/d http://onsemi.com 5 the previous default has disappeared and the converter is stabilized. however, the designer shall keep in mind that injecting a compensation ramp diminishes the current loop gain. this has the same effect as raising rsense on the smallsignal point of view. as a result, the controller grows its operating feedback voltage v fb (that sets ip) to impose the same peak current. if before compensation v fb was already close to the maximum limit, the ramp injection will make it raise and the possibility exists that the ncp1200 goes into shortcircuit protection (v fb 4.1 v). we deliberately selected a rather high value for the ramp generator resistor in order to not load the ncp1200 (otherwise the standby power can be degraded). as a consequence, the summing resistor rcomp cannot be too low to prevent from disturbing the ramp generator. in a noisy environment, the electrical paths conveying these signals to the ncp1200 pins shall be kept as short as possible to avoid undesirable peaking. in case of troubles, the solutions consists in lowering the ramp generator's output impedance and reiterating the other elements. references 1. r. b. ridley, aa new smallsignal model for currentmode control'', phd. dissertation, virginia polytechnic institute and state university, 1990 (email : rridley@aol.com). this document can also be ordered from ray ridley's homepage: http://www.ridleyengineering.com/index.html 2. holland, amodelling, analysis and compensation of the current mode convertero, powercon 11, 1984 record, paper h2.
and8029/d http://onsemi.com 6 notes
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